本書較為全面地論述了計(jì)算機(jī)組織與結(jié)構(gòu)的基礎(chǔ)原理，所講述的內(nèi)容與當(dāng)前的一些實(shí)際設(shè)計(jì)問(wèn)題聯(lián)系密切。全書共分五大部分，包括緒論、計(jì)算機(jī)系統(tǒng)、通用處理單元、控制單元以及并行組織，附錄包括數(shù)字邏輯、教學(xué)指導(dǎo)，書末附有詞匯表、索引頁(yè)。另外，每章均列有參考文獻(xiàn)與Web站點(diǎn)，方便讀者查詢相關(guān)資料?？紤]到計(jì)算機(jī)層次化的組織結(jié)構(gòu)，本書在內(nèi)容組織上也采用了同樣的方式：計(jì)算機(jī)系統(tǒng)→處理器→控制單元。這種方式符合人們通常的思維習(xí)慣，便于讀者理解和學(xué)習(xí)。本書為第五版，作者William Stallings在前幾版的基礎(chǔ)上做了大量的優(yōu)化和改進(jìn)，并增加了許多新的內(nèi)容，諸如光存儲(chǔ)器、超標(biāo)量設(shè)計(jì)、多媒體指令集、同步多處理器等，體現(xiàn)了計(jì)算機(jī)組織結(jié)構(gòu)發(fā)展的最新技術(shù)。 本書可作為電子、計(jì)算機(jī)專業(yè)本科和研究生的教材，也可供工程技術(shù)人員參考使用。 內(nèi)容：1. 緒論（導(dǎo)言，計(jì)算機(jī)發(fā)展與性能）2. 計(jì)算機(jī)系統(tǒng)（系統(tǒng)總線，內(nèi)部存儲(chǔ)器，外部存儲(chǔ)器，輸入/輸出系統(tǒng)，操作系統(tǒng)支持）3. 通用處理單元（計(jì)算機(jī)運(yùn)算，指令集特性與功能，指令集編址模式，CPU結(jié)構(gòu)與功能，精簡(jiǎn)指令集計(jì)算機(jī)，指令級(jí)并行與超標(biāo)量處理機(jī)）4. 控制單元（控制單元操作，微程序控制）5. 并行組織（并行處理）附錄A 數(shù)字邏輯 附錄B 計(jì)算機(jī)組織與結(jié)構(gòu)教學(xué)指導(dǎo) 詞匯表 參考文獻(xiàn) 索引 作者簡(jiǎn)介：William Stallings has made a uhique contribution to understanding the broad sweep of technical developments in computer networking and computer architecture.He has authored17 titles，plus revised editions，for a total of 37 books on various of these subjects.He has three times received the award for best Computer Science Textbook of the Year from the Text and Academic Authors Association.
Web Site Preface PART1 OVERVIEW Chapter 1 Introduction 1.1 Organization and Architecture 1.2 Structure and Function 1.3 Outline of the Book 1.4 Internet and Web Resources Chapter 2 Computer Evolution and Performance 2.1 A Brief History of Computers 2.2 Designing for Performance 2.3 Pentium and PowerPC Evolution 2.4 Recommended Reading and Web Sites 2.5 Problems PART II THE COMPUTER SYSTEM Chapter 3 System Buses 3.l Computer Components 3.2 Computer Function 3.3 Interconnection Structures 3.4 Bus interconnection 3.5 PCI 3.6 Recommended Reading and Web Sites 3.7 Problems Appendix 3A: Timing Diagrams Chapter 4 Internal Memory 4.1 Computer Memory System Overview 4.2 Semiconductor Main Memory 4.3 Cache Memory 4.4 Pentium II and Power PC Cache Organizations 4.5 Advanced DRAM Organization 4.6 Recommended Reading and Web Sites 4.7 Problems Appendix 4A: Performance Characteristics of Two-Level Memories Chapter 5 External Memory 5.1 Magnetic Disk 5.2 RAID 5.3 Optical Memory 5.4 Magnetic Tape 5.5 Recommended Reading and Web Sites 5.6 Problems Chapter 6 Input/Output 6.1 External Devices 6.2 I/O Modules 6.3 Programmed I/O 6.4 Interrupt-Driven I/O 6.5 Direct Memory Access 6.6 I/O Channels and Processors 6.7 The External interface: SCSI and FireWire 6.8 Recommended Reading and Web Sites 6.9 Problems Chapter 7 Operating System Support 7.1 Operating System Overview 7.2 Scheduling 7.3 Memory Management 7.4 Pentium II and Power PC Memory Management 7.5 Recommended Reading and Web Sites 7.6 Problems PART III THE CENTRAL PROCESSING UNIT Chapter 8 Computer Arithmetic Chapter 9 Instruction Sets: Characteristics and Functions Chapter 10 Instruction Sets: Addressing Modes and Formats Chapter 11 CPU Structure and Function Chapter 12 Reduced instruction Set Computers Chapter 13 Instruction-Level Parallelism and Superscalar Processors PART IV THE CONTROI UNIT Chapter 14 Control Unit Operation Chapter 15 Microprogrammed Control PART V PARALLEL ORGANIZATION Chapter 16 Parallel Processing Appendix A Digital Logic Appendix B Projects for Teaching Computer Organization and Architecture Glossary References Index
鄂公網(wǎng)安備 42010302001612號(hào) 